• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A method for transmitting/receiving a digital data at high-speed is provided to divide a high frequency digital data by 4-bit, performs a coding by using 5-bit, and reduce an interference effect between signals. CONSTITUTION: A digital data of an input specific unit bit is divided by 4-bit unit of D1,D2,D3,D4. A coding process is performed by 5-bit unit of M1,M2,M3,M4,M5, and a transmission process is performed. A coded signal is received by 5-bit unit of M1,M2,M3,M4,M5, and decoded as a data of 4-bit unit of D1,D2,D3,D4. Thereby, method for transmitting/receiving a digital data at high speed reduces an interference effect between signals.
    公开号:KR20000027882A
    申请号:KR1019980045926
    申请日:1998-10-29
    公开日:2000-05-15
    发明作者:문홍식
    申请人:김영환；현대반도체 주식회사；
    IPC主号:
    专利说明:

    High speed transmission / reception method of digital data
    The present invention relates to the transmission and reception of digital data, and more particularly, to a high-speed transmission and reception method of digital data suitable for reducing interference between signals generated during transmission of a high frequency digital signal through a transmission line.
    In general, high-speed transmission of digital data mainly uses differential signals with reduced signal levels. However, when trying to transmit at higher speed, the transmission speed is limited due to interference between high frequency signals.
    Therefore, a method of encoding a signal component having a lower frequency component has been proposed as a method to solve this problem.
    This is typically used in the link part where a device such as a liquid crystal display receives a signal.
    In this case, this baud rate determines the resolution of the display.
    In the conventional digital data transmission / reception method, a circuit for connecting a panel display for converting a digital signal without an encoding process is used.
    That is, the conventional digital data transmission / reception method transmits and receives data using only a circuit converting a differential signal (LVDS: Low Voltage Differential Signal) to serially transmit each 8-bit R, G, and B data.
    As described above, the conventional digital data transmission / reception method uses only a circuit converting into a differential signal, and thus, a transmission rate per channel (generally 300 μbit / s or more) cannot be transmitted above a certain level due to interference between transmission lines. .
    Therefore, first, it is required to reduce the high frequency component of the signal by reducing the level change of the digital signal through the encoding of the digital signal to be transmitted.
    However, such a conventional method of transmitting and receiving digital data has the following problems.
    That is, in the conventional case, transmission is performed only by a differential signal of a low signal level without protection conversion, and transmission of a predetermined speed or more is limited due to signal interference.In the encoding method, the encoding is performed by successive XOR results such as XOR. Along with the delay of the transmission time, a complicated encoding and decoding circuit is required.
    The present invention has been made to solve the above problems and provides a high-speed transmission and reception method of digital data to reduce the interference effect between the signals generated during transmission by encoding the high-frequency digital data to be transmitted through the transmission line by 4 bits divided by 4 bits Its purpose is to.
    1 is a code illustrating encoding 4-bit data into 5-bit data according to the present invention.
    2A is a logic function of encoding 4-bit data into 5-bit data according to the present invention.
    2B is a logic function obtained by decoding 5-bit data into 4-bit data according to the present invention.
    3 is a block diagram showing an example of 8-bit data transmission according to the present invention.
    Explanation of symbols for main parts of the drawings
    20: multiplexer 30: code generation unit
    40: serial transmission and differential signal generation unit
    As described above, the high-speed transmission / reception method of digital data according to the present invention divides the digital data of a specific unit bit input into four bit units of D1, D2, D3, and D4, and the divided D1, D2, D3, and D4. Encoding and transmitting data in 5-bit units of M1, M2, M3, M4, and M5 using 4-bit data; and receiving the signal encoded in 5-bit units of M1, M2, M3, M4, and M5, and receiving D1. And decoding the data into 4-bit units of D2, D3, and D4.
    Hereinafter, a high speed transmission / reception method of digital data according to the present invention will be described in detail with reference to the accompanying drawings.
    1 is a code illustrating encoding 4-bit data into 5-bit data according to the present invention, FIG. 2A is a logic function of encoding 4-bit data into 5-bit data according to the present invention, and FIG. Logical function obtained by decoding 5-bit data into 4-bit data.
    In general, in order to transmit a digital signal at high speed, a differential signal having a small amplitude is required, and encoding at the transmitter and a decoder at the receiver are required to reduce data errors due to interference between high frequency signals.
    However, when the encoding and decoding parts are complicated, the signal connection part, which is an accessory circuit, becomes large when the chip is implemented, and the delay of the initial transmission time is a problem in serial transmission using a pipeline as a time delay for encoding. .
    In order to solve this problem, a code having a similar form between codes is coded as shown in FIG.
    That is, the code of FIG. 1 encodes a signal to be transmitted by 5 bits in units of 4 bits to reduce signal interference by using a high speed serial transmission over a small channel.
    First, arrange as "0" or "1" consecutively so that there is little level change in the code, and when changing the code between the codes, "1" or "0" is continuous so that the level change of the code transmitted through the whole serial is small. To be configured.
    In addition, the "0" and "1" of probabilistic consecutive codes are equally arranged to obtain a DC balance effect in terms of transmitted energy.
    On the other hand, as shown in Figure 1, the four-bit (D1, D2, D3, D4) of the digital data is encoded into a five-bit (M1, M2, M3, M4, M5) data code, the encoded 5-bit data code The 4-bit data is arranged so that the level change is minimized and corresponds to the 4-bit data 1: 1.
    Each code coded by 5 bits as described above has a maximum of two level changes, and half has only one level change.
    Therefore, the case of serial transmission reduces the likelihood of a bell change occurring between the cord and the connecting part of the cord. In addition, some DC balance is achieved in the cord, reducing the need for additional DC balanced circuits in the cord that are connected in series.
    In the case of configuring the encoding for implementing the code as described above and decoding the received data and restoring it back to the original digital data, several logic gates can be configured due to the similarity between the codes.
    That is, the logic function of FIG.With M1,By the operation of M2,The operation of encodes M3, D3 to M4, and D4 to M5.
    As described above, the 4-bit data of D1, D2, D3, and D4 is encoded into 5-bit data of M1, M2, M3, M4, and M5, and then transmitted. In other words,To calculate D1,Decode by D2, M4 by D3, and M5 by D4 into 4 bits of data, respectively.
    As described above, since the code / decoding consists of several logic gates, the area of the encoder requiring integration in the chip and the decoder integrated in the receiver can be reduced.
    Therefore, in the case of 8-bit data of R, G, and B, such as a liquid crystal display device, using 4-bit digital coded code, 4-bit digital data is divided into 4 bits and encoded into 5 bits to be directly converted into a pipeline. It can be transmitted quickly while reducing signal interference.
    In particular, a code in which 4-bit data is encoded into 5-bit data can be effectively applied when high-speed transmission is required in short transmissions in which repetitive digital data of short length is dense.
    3 is a block diagram showing an example of transmission of 8-bit data according to the present invention.
    As shown in FIG. 3, 8-bit data to be transmitted through a transmission line is divided into four bits and input to a multiplexer (MUX) 20, and the multiplexer 20 is 4-bit data by an external clock signal CK. Outputs
    Subsequently, the 4-bit data output from the multiplexer 20 is input to the code generator 30 to be encoded into 5 bits to output 5-bit data.
    The 5-bit data output from the code generator 30 is input to the serial transmission and differential signal generator 40 to complete the data transmission through the transmission line.
    As described above, the method of encoding / decoding digital data for high-speed transmission and reception according to the present invention has the following effects.
    That is, when decoding digital data to be transmitted by encoding 4-bit digital data into 5-bit data, the interference effect between high frequency signals, which is a problem in high-speed serial transmission of digital data, can be effectively reduced. The circuit configuration is relatively simpler than a complicated encoding method and can be transmitted at high speed.
    权利要求:
    Claims (3)
    [1" claim-type="Currently amended] Dividing the digital data of a specific unit bit input into 4 bit units of D1, D2, D3, and D4;
    Encoding and transmitting the data in four bit units of M1, M2, M3, M4, and M5 using the divided 4-bit data of D1, D2, D3, and D4;
    Receiving a signal encoded in 5-bit units of M1, M2, M3, M4, and M5, and decoding the data into 4-bit units of D1, D2, D3, and D4. How to send and receive.
    [2" claim-type="Currently amended] The method of claim 1,
    By encoding and transmitting the divided 4-bit data of D1, D2, D3, and D4 in 5-bit units of M1, M2, M3, M4, and M5,With M1,By the operation of M2,And M3, D3 to M4, and D4 to M5, respectively.
    [3" claim-type="Currently amended] The method of claim 1,
    Receiving the signal encoded in 5-bit units of M1, M2, M3, M4, M5 and decoding the data into 4-bit units of D1, D2, D3, D4To calculate D1,And decoding D2, M4 to D3, and M5 to D4 into 4 bits of data, respectively.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-10-29|Application filed by 김영환, 현대반도체 주식회사
    1998-10-29|Priority to KR1019980045926A
    2000-05-15|Publication of KR20000027882A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980045926A|KR20000027882A|1998-10-29|1998-10-29|Method for transmitting/receiving digital data at high speed|
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